FIN-FET DEVICE

Introduction

FinFET which is typically termed as Fin Field Effect Transistor is a 3D or a non-planar transistor which is used for the purpose of designing modern processors. Initially, the designing of planar used to be built on silicon on insulator (SOI) substrate. Regardless of that, the designing of FinFET also makes use of the conducting channels which emanates above the level of such an insulator hence creating a thin structure of silicon which shape of a fin termed as a gate electrode (Colinge, 2008). It is this fin-shaped electrode which enables the operation of multiple gates on a single transistor.

On the other hand, what is noted is that the process of this multi-gate extends the Moore’s law thus enabling the manufactures of all types of semiconductors to be in the position of developing CPUs (central processing units) as well as memory modules which are relatively smaller, quick performance and consuming less energy.

History

Basically, the FinFET was initially invented for the manufacture of self-aligned duo-gate MOSFETS. The reason for this is because it is the one which was to be used for the purpose of addressing the need of improving the controlling of the gates in order to suppress DIBL, IOFF as well as process induced variability for the Lg<25nm. Moreover, the Bulk and the Tri-Gate variations of the entire FinFet was in return manufactures for the need of improving the cost and manufacturability.

With respect to that, it should be noted that the technology has taken 10 years for its manufactures to bring into existence or production of the 3-D transistors. With this success, it is realized that the multi-gate MOSFETs has the ability of providing a route or a pathway which achieves a lower power consumption rate and /or improved performance (Han & Wang, 2013).  Conversely, with this success, it is noted that further evolution of this MOSFET technology to the entire stacked-channel structure may typically evolve at the end of the roadmap.

Modeling

In 2012, the UC Berkeley BSIM Group ended up releasing a BSIMCMG106.0.0. This was perceived as being the first FinFET model to be invented. The reason for its manufacture is because, the BSIM-CMG was originally implemented in Verilog-A. Therefore, its physical surface potential based formulations were obtained for not only the intrinsic but also the extrinsic models which comprised of finite body doping. At its source, the surface potential as well as the drain ends remains to be solved analytically through the quantum and poly-depletion mechanical effects (Han & Wang, 2013).  The effects which come from this minute body doping remains to be captured through the perturbation approach. The reason for this in the long run is because it’s the analytic surface potential solution which ends up agreeing closely with all the 2-D device simulation results (Colinge, 2008). For instance, in case the doping concentration channel is low to the extent of being neglected, it then means that some computational efficiency has to be improved further through setting a specific flag for i.e. (COREMOD=1)

Nonetheless, at the end, the essential multi-gate (MG) transistor behaviors will be captured through this model. In the solution of the Poisson’s equation, the inversion of volume is included thus making the subsequent I-V formulation to capture the effect of volume inversion automatically. In the body of the MG MOSFETSs, the general analysis of the electro-static potential is the one which ultimately offers the model equation for the SCE termed as (short-channel effects). Thus, the additional electrostatic control which comes from the top/bottom gates or the triple/quadruple gate (end-gates) remains to be captured in the short channel models of this system.

Fabrication

A new complementary metal oxide semiconductor (CMOS) which is perceived as being compatible with the Bulk-Si FinFETs fabrication process currently has been manufactured. Comparing it with the contemporary fabrication processes regarding the SOI mentioned above as well as the Bulk-Si FinFET, what has been realized is that this modern approach is relatively simpler and less costly.

Thus, with any form of high performing CMOS-Si FinFETS, the fin which is isolated to the whole Si substrate through the oxide have currently remained to be fabricated through the use of this modern approach. For example, with low body concertration of about (1x15cm⁻³), the whole of the PMOS will end up indicating I_on/I_off ratio of about 10⁴ as well as a short channel behavior which comprises of a SS (subthreshold swing) of about 280 mV/dec or a drain induced barrier lowering (DIBL) of 258mV/V (Han & Wang, 2013).

Simulation

After the generation of a meshed structure through simulation, the next step is the simulation of the device. The simulation of the device is performed through the invoking suitable transport model. The reason for this is because the predictable drift-diffusion model which was typically used as the transport model was never sufficient when it comes to the capturing of the SCEs in the nanometer FinFETs and MOSFETS. The quantum corrections with is associated with the hydrodynamic model for instance density model nowadays has remained to be a popular model amongst the FinFET device simulation (101) researches (I.C.S.S.P.D, 2007). In sequence, simulation circuits which have multiple strategies which of course enable the mixed model simulation of the device.

What this means is that the individual FinFET device is usually connected using cables externally or else other circuit elements which in the long-run forms a netlist as well as combined transport equations which will be solved on the whole netlist. This is to say that it is this feature which will allow the engineers of the device to speculate the extent at which the device will.

Performance

With respect to the performance of the device, at the level of 22nm node, it is estimated that the superior electrostatic as well as the reduced junction capacitance in the respective FinFET would offer a 13-23 percentage reduction in its delay respect to the planar FETs (I.C.S.S.P.D, 2007). Nvertheless, the advantage which comes from this is that it is to be offset through the enhancement of the Cgs (gate-to-source or drain capacitance) in the FinFETs. In this category, the capacitance at the level of 22nm dimensions of the FinFETs  which determines its optimization can be limited  to < 6% hence resulting into the overall advantage which will be up to 17 percentage over the planer technology.

Market

With the market viability of the device, it means that still there are fewer player who are expected to be in the position of delivering the manufacture of the FinFET technology in some years to come. This is to say that there will be two dedicated foundries and IDM/founders (Jerry et al, 2013).

Moreover, in the next few year it means that that the only player in the will be the above. Due to the electronic shift in the market demand for the tablets and smartphones, the entire technology will be applied to the bigger duty unlike the technology itself.

Reliability

In respect to that, the thermal reliability analysis has remained to be the integral portion of the integrated circuit (IC) design ecosystem. With the existence of the FinFET technology node in the mainstream, the empirical models from its foundries will be combined with the whole analysis of the IC-package in order to gain the thermal profiles with the micro resolution (Jerry et al, 2013).

This then means that the reliability of its verification is regarded as the example of the shift to the entire thermal-aware signoff or analysis. Thus the package thermal model with respect to the spatial accuracy of the device is the one which has the ability of bringing newer levels of accuracy which stimulates passively cooled electrical subsystems.

Vendors

The leading-edge foundry business of this device is challenging. For its starters, it is noted that the foundry vendors will need to have diversified resources as well as the technical know-how.  Although it appears that it will be ultimately difficult to make cash in this business, the foundry vendors are currently making some extreme 16nm/nm FinFET processes in the whole market.

Besides that, the industry is still facing a lot of challenges at about 10nm according to the report from the industry itself (F.E.M. L, 2015). For instance, TSMC and Samsung currently are accelerating the whole of their perspective of the 10nm FinFET efforts.

Design issues – minimizing impacts

Due to the fact that the designers of the device are increasingly careless about it, the energy efficiency of the device with the quoting channel lengths is nowadays becoming relatively less relevant. Thus given the availability of the transistors per unit area, its designers will be motivated to the extent of using multi-processors at its lower voltage. The importance of that it is because it will obtain the same voltage at the similar voltage regardless of the number of processors at either low or high voltage (F.E.M. L, 2015).  

Moreover, it’s because the founders of this device desires to make the transition of the FinFET process smooth and transparent to its designing community. Thus the IP and the EDA industries of this device will be force to the work beyond that in order to understand the complexities involved in it. In other words, they will have to make the advantage of its area of benefit, power consumption, and performance while still obtaining the painless costs and the market quickly through the same process of inventing as well as passing it to its implementation process.

Power

With its rate of power consumption, its metric performance per unit power in designing the optional FinFET device as compared to the contemporary technology is perceived as being a better performance is association with its power budget or typically at lower levels (Colinge, 2008). This is to say that in terms of power consumption, it is better improved device as compared to the planar device originally used. Regardless of the wrapping of the gate and channel used around it, the FinFETs ends up creating a depleted channel which in return has the ability of reducing the leakage problem of the whole planar transistors. This results to a lower supply of voltage and threshold frequency.

 

 

 

 

 

Reference

Colinge, J.-P. (2008). FinFETs and other multi-gate transistors. New York: Springer.

Han, W., & Wang, Z. M. (2013). Toward Quantum FinFET. Cham: Imprint: Springer.

International Conference on Simulation of Semiconductor Processes and Devices, Grasser, T., & Selberherr, S. (2007). Simulation of semiconductor processes and devices, 2007: SISPAD 2007. Wien: Springer Verlag.

FinFET: Extending Moore's Law (2015). FinFET: Extending Moore's Law. LexInnova Technologies,

Jerry G, Fossum, Vishal & Trivedi P, (2013). Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs. Cambridge University Press.